1. Field of the Invention
This invention relates to the testing of electronic circuits and, more specifically, to the use of scan based testing.
2. Description of the Relevant Art As the gate and pin counts of integrated circuits has grown, device-level testing of integrated circuits has become increasingly difficult. Subsequent to manufacture, access to the internal circuitry of a device (or “chip”) may be limited. In many cases, access to a chip's circuitry is only available at its boundary through its external pins. Scan based techniques are one technique utilized to test integrated circuits with large gate and pin counts.
Scan techniques include boundary scan testing and internal scan testing. Boundary scan testing generally occurs at the boundary between the core logic of a device and its external pin connections. A device configured for boundary scan typically includes boundary scan cells, each of which is located between a signal pin and the core logic of the device. A plurality of these boundary scan cells may be connected together to form a boundary scan chain, or path. On the other hand, internal scan testing generally involves partitioning a chips logic into individually testable units. FIG. 1 is an illustration of an exemplary integrated circuit (IC) 100 configured for boundary scan testing. The IC 100 includes a plurality of boundary scan cells chained together. During normal IC 100 operations, data may pass unaffected through the boundary scan cells between the core logic and signal pins. During boundary scan test operations, test data may enter the IC 100 through the TDI (Test Data In) pin 110, and pass through the chain of boundary scan cells, leaving the chip through the TDO (Test Data Out) pin 120. The path 130 the test data traverses is also illustrated. In effect, the chain of boundary scan cells acts as a shift register, as data bits may be shifted from one cell to the next.
The state of each boundary scan cell may be monitored during scan shifting through those signal pins associated with an output or bi-directional signal. For example, during boundary scan testing of the exemplary IC 100 shown in FIG. 1 (assuming all pins are bi-directional), the state of each boundary scan cell may be monitored by automated test equipment (ATE) through its associated signal pin as data bits are shifted through the boundary scan path 130. During the shifting of data through the boundary scan path 130, each cell will typically make several transitions between a logic high level and a logic low level. If a defect is present (such as an unsoldered signal pin), the ATE may not detect the expected state for the given cell at a given time, thereby causing a test failure. In this manner, a defective signal connection may be detected. For input signals, test data may be driven into a boundary scan cell through its associated signal pin, and may be monitored through the TDO pin 120 after shifting it through the scan chain.
As already noted, often times scan testing is configured wherein the scan chains of a number of blocks in a device are coupled together. To this end, longer, scan paths may be created by coupling the TDO output of one scan block to the TDI input of another. FIG. 2 is a block diagram of a single scan path. In the drawing, a plurality of scan blocks 210A–210C are chained together by coupling TDO outputs to TDI inputs. A TMS (Test Mode Select) signal is used to place the chips in a test mode, while the TCK (Test Clock) provides the necessary clock signal for shifting data through the scan chain. Elements referred to herein with a particular reference number followed by a letter will be collectively referred to by the reference number alone. For example, scan blocks 210A–210C will be collectively referred to as scan blocks 210.
In a chip composed of hierarchical blocks with separate scan chains, it can be very difficult to coordinate the scan out of the full state of the chip when the blocks share a common scan clock. FIG. 2 illustrates one embodiment of a device 200 configured for internal scan testing. FIG. 2 shows five partitions 210A–210E which are each configured for scan testing. A control unit 290 is configured to control the scan chains for each of the partitions 210. In the embodiment shown, the control unit 290 is configured to convey a common scan clock signal 230 to all partitions 210. Also shown is a test mode signal 240 which may be used to indicate the mode of operation for each partition, normal or test. As seen in FIG. 2, each partition is coupled to the control unit 290 via two buses, 220 and 221. A first bus 220 is configured to convey test data to each partition, while the second bus 221 is configured to convey scan test data back to the control unit 290.
Generally speaking, each partition 210 includes a number of scan cells configured as a chain. Application of the scan clock 230 causes the data within the chain to shift by one scan cell. Because a common scan clock 230 is used by each of the partitions, coordinating the scan out of test data can be extremely difficult. While the internal state for one partition is being scanned out, the data within other partitions is also being clocked resulting in a loss of their state. Consequently, without gating the scan clock to each block, or creating separate scan clocks for each block, it is difficult to avoid this loss of state.